Now there is a way to statically analyze the cache behavior of your tasks.
aiCache is a tool for predicting a program’s intrinsic instruction cache behavior. In other words, aiCache classifies most references to the instruction memory (instruction fetches) as cache hits or misses.
Features
- Directly analyzes executables: no special compiler or linker required
- Customizable cache geometry: various cache architectures supported
- Selectable start point enables the program parts of interest to be focused on
- Interprocedural analysis methods enable the cache behavior of different executions of an instruction to be distinguished
- Virtual loop transformation allows the cache behavior of the first execution of an instruction in a loop to be distinguished from all others
- Persistence analysis determines whether instructions will survive in the cache, i.e. whether they are persistent. This analysis can be used in addition to the standard analysis
- Conflicting instructions: for every unclassified instruction, any instructions which might be in the cache and lead to a possible replacement of that instruction can be shown. This information can be used to find a better memory layout for your code
Why do you need aiCache?
- Cache behavior has to be taken into account in order to predict
the execution time of your code
There is a tremendous gap between the cycle times of modern microprocessors and the access times of main memory. Cache memories usually work without any hitches, yet under some circumstances minimal changes in the program code or program input may lead to dramatic changes in cache behavior.
aiCache determines the worst-case intrinsic cache behavior of your task. It allows you to check for the absence of cache conflicts affecting the time-critical parts of your code.
- Current tools are not always able to accurately predict cache behavior
The widely used classical methods of predicting execution times are not generally applicable. Software monitoring or the dual loop benchmark changes the code, in the process influencing cache behavior. Hardware simulation, emulation, or direct measurement using logic analyzers can only determine the execution time for one input.
The predictions of aiCache are valid for all inputs.
Categorization of memory references
aiCache determines a categorization for each instruction from the control flow graph of the program.
| Category | Abbr. | Meaning |
|---|---|---|
| always hit | ah |
The memory reference always results in a cache hit. |
| always miss | am |
The memory reference always results in a cache miss. |
| persistent | ps |
The referenced memory block is loaded once at most. |
| unreachable | un |
The code cannot be reached. |
| not classified | nc |
The memory reference couldn't be classified as
ah,
am,
ps, or
un. |
Representation of analysis results
The results can be produced in HTML to allow for convenient browsing. The left window shows the execution contexts which are distinguished and which correspond to a path in the call graph. The right window shows the categorization of the instructions of the function in the corresponding context.
Platforms, targets, trial version
With the launch of the aiT WCET Analyzers product line, aiCache is no longer available as a stand-alone product. Cache analysis has been fully integrated into aiT. Evaluation versions are available for a growing number of target processor architectures. Please contact us for further information.
Links
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